Semiconductor devices are employed in many types of equipment to perform a wide variety of applications. An important type of semiconductor device for use in the memory field is known as dynamic random access memory (DRAM). DRAM is extensively used for memory in computers. A basic DRAM cell may include a capacitor and a transistor formed in a semiconductor substrate. The capacitor stores a charge representing data. The transistor allows the data to be refreshed, read from, or written to the capacitor. By reducing the surface area of the capacitor or the transistor, more DRAM cells can fit onto a chip. The increase in the amount of DRAM cells results in greater memory capacity for the chip.
One method of minimizing the surface area of a DRAM cell is to vertically construct the components (i.e., where a semiconductor device includes components formed at several or more layers thereof). One way to accomplish such vertical construction may involve forming a trench in a semiconductor substrate. For example, a dielectric film may be deposited over the sides of the trench. Then, polysilicon may be deposited on the dielectric film, acting as one of the electrodes of the capacitor. A recess may be created in the polysilicon by removing a portion of the polysilicon through an etching process. Layers of conductive, semiconductive and/or insulating material can then be deposited in the recessed area of the polysilicon. The steps of etching the polysilicon and depositing new material can be repeated until the desired component is formed.
As the surface area of a memory cell is made smaller, and higher DRAM density is achieved, the trench area in which capacitors are formed may be reduced. Doped silicon (Si) and other semiconductor materials (i.e., xe2x80x9cfill materialxe2x80x9d) are often filled into the trench and become part of the capacitor. For example, a memory cell fabricated as part of a 4 Mbyte DRAM chip may have a trench area of about 11.3 xcexcM2. A memory cell fabricated as part of a 256 Mbyte DRAM chip may have a trench area of about 0.6 xcexcm2. Similarly, a memory cell fabricated for use in a 1 Gbyte DRAM chip may have a trench area of about 0.32 xcexcm2. Thus, the area of the trench typically, but not always, decreases as the memory capacity of the DRAM chip increases.
In order to compensate for the reduced surface area of a DRAM cell, trenches may be formed relatively deep into the substrate, for example between 4-8 xcexcm below the substrate surface. This will permit the total area of the trench to remain the same, or even increase, when compared to a shallower but wider trench.
Deeper trenches are typically said to have a high aspect ratio. The xe2x80x9caspect ratioxe2x80x9d is the ratio of the depth of a trench compared to the width of the opening at the top of the trench. For example, memory cells fabricated as part of a 256 Mbyte DRAM chip may include trench capacitors having an aspect ratio of between 10:1 and 20:1. This means that the depth of the trench walls is between 10 and 20 times greater than the width of the trench opening. In higher density DRAM chips, such as chips of 1 Gbyte or more, a typical trench aspect ratio may be on the order of 40:1 to 60:1 or higher. In such high aspect ratio situations, the trenches are typically very narrow. The very narrow trenches impact not only the thickness of the fill material of the capacitor, but also how the fill material is formed in the trench.
Capacitance and resistivity are important parameters that affect memory cell operation. For instance, the capacitance of the memory cell may need to remain above a certain level in order for the cell to store charge effectively. In particular, the cell may need to maintain a capacitance on the order of 25 fF. If the capacitance falls significantly below this level, the cell may discharge too rapidly and the data stored by the cell can be lost.
Resistivity needs to be as low as possible in order to effectively charge the capacitor. Preferably, the resistivity is below about 5,000 xcexcxcexa9xc2x7cm. In low aspect ratio trenches, fill material layers having about 100 nm thickness could be formed on the dielectric film, commonly known as a node dielectric, which lines the trench sidewalls while maintaining the resistivity of about 5,000 xcexcxcexa9xc2x7cm. However, the high aspect ratios of high-density DRAM designs require much thinner fill layers having a lower resistivity level.
Increasing the dopant concentration of the fill material acts to lower resistivity. A method of doping Si is to apply a layer of Si to the node dielectric lining the trench sidewalls, followed by a layer of dopant over of the Si. The dopant can be diffused into the Si by heating, or annealing, the two layers, for instance, in a later step in the process of forming an electrode the DRAM memory cell. One problem with this layering scheme in high aspect ratio trenches is the necessity of forming thin layers of material on the trench sidewalls while maintaining an adequate level of resistivity. Therefore, a need exists for improved capacitor fill material having narrow thickness. A need also exists for improved methods of forming the fill material with a high concentration of uniformly distributed dopant therein.
The present invention provides a fill material having a resistivity suitable for use in a capacitor. In one embodiment, a semiconductor device includes a semiconductor substrate, a transistor, and a capacitor formed in the substrate. The capacitor is electrically connected to the transistor. The capacitor is formed in a trench defined by sidewalls having a depth and a top opening having a width. A dielectric material lines a portion of the sidewalls. A layer of fill material is arranged on the dielectric material. The fill material includes a semiconductor base material and a dopant, and has a resistivity below 5,000 xcexcxcexa9xc2x7cm.
The depth of the sidewalls relative to the width of the top opening defines an aspect ratio of the trench. In one preferred embodiment, the aspect ratio is at least 20:1. More preferably, the depth of the sidewalls is between 4 to 8 xcexcm and the aspect ratio is between 40:1 and 60:1.
In another preferred embodiment, the dopant may be selected from the group consisting of As, Sb and P. Similarly, the base material may be selected from the group of Si and SiGe. The dopant concentration is preferably at least 1xc3x971017.
In accordance with another aspect of the present invention, a method of fabricating a semiconductor device is provided. The method includes forming a trench in a semiconductor substrate. The trench includes sidewalls defining a trench depth and a top opening defining a trench width. The sidewalls may be substantially covered with a dielectric material. A fill material having a resistivity below 5,000 xcexcxcexa9xc2x7cm is deposited on the dielectric material. Deposition is preferably performed by flowing a first gas and a second gas together over the trench at a selected temperature and pressure. The first gas includes a base material and the second gas includes a dopant. Flowing the first and second gasses together facilitates in situ doping of the base material.
In one preferred embodiment, the selected temperature is between 400xc2x0 C. and 700xc2x0 C. More preferably, the selected temperature is between 500xc2x0 C. and 600xc2x0 C. It is also preferable for the selected pressure is between 100 Torr and 1000 Torr.
The method may further comprise applying a relatively low temperature proximate to a top surface of the semiconductor substrate and a relatively high temperature proximate to a bottom surface of the semiconductor substrate. The temperature difference between the top and bottom surfaces may reduce bread loafing and to improve conformality.
In a preferred embodiment, the base material is Si, and the first gas is selected from the group consisting of SiH4, Si2H6, TCS, DCS and HDS.
In another preferred method, the fill material is formed by depositing a base layer on the dielectric material. The base layer is preferably less than 50 nm thick. Then, the base layer may be soaked with a gas containing a dopant at a second temperature and a second pressure until the base layer is coated with the dopant.
Preferably, the method includes repeating forming the base layer and soaking the base layer between one and five times. In another example, the method includes forming a capping layer over the fill material. The capping layer minimizes out-diffusion of the dopant.
The method preferably includes annealing the semiconductor substrate such that the dopant migrates into the base layer. In yet another example of the invention, the second temperature is between 500xc2x0 C. and 650xc2x0 C. and the second pressure is between 50 mTorr and 760 mTorr.
The method of fabricating a semiconductor device may comprise forming the fill material by depositing a base layer on the dielectric material and diffusing a dopant into the base layer at a second temperature and a second pressure. The base layer thickness may be less than 50 nm.
In one example, the first temperature is between 500xc2x0 C. and 650xc2x0 C. and the first pressure is between 50 mTorr and 760 mTorr. In another example, the second temperature is between 850xc2x0 C. and 1100xc2x0 C., and the second pressure is between 1 Torr and 100 Torr.
In another preferred method of fabricating a semiconductor device, a first fill material is formed over dielectric material in a lower region of a trench, and a second fill material is formed in an upper region of the trench. The first fill material includes a light dopant. The second fill material includes a heavy dopant. The heavy dopant reduces diffusion of the light dopant out of the trench. The combination of the first and second fill materials has a resistivity of below about 5,000 xcexcxcexa9xc2x7cm.
In one example, the first fill material is formed by flowing a first base gas and a first dopant gas together over the trench at a first selected temperature and pressure. The first base gas includes a first base material. The first dopant gas includes a light dopant. Flowing the first base gas and first dopant gas together facilitates in situ doping of the first base material. Similarly, the second fill material is formed by flowing a second base gas and a second base material together over the trench at a second selected temperature and pressure. The second base gas includes a second base material. The second dopant gas includes the heavy dopant. Flowing the second base gas and the second dopant gas together facilitates in situ doping of the second base material.
In another example, the first fill material is formed by depositing a first base layer on the dielectric material and soaking the first base layer with a first dopant gas containing the light dopant at a first selected temperature and pressure until the first base layer is coated with the light dopant. The second fill material is formed by depositing a second base layer over the first fill material and soaking the second base layer with a second dopant gas containing the heavy dopant at a second selected temperature and pressure until the second base layer is coated with the heavy dopant.
In another example, the first fill material is formed by depositing a first base layer on the dielectric material and diffusing the light dopant into the first base layer at a first selected temperature and pressure. The second fill material is formed by depositing a second base layer over the first fill material and diffusing the heavy dopant into the second base layer at a second selected temperature and pressure. Preferably, the method further includes forming a capping layer over the second fill material and annealing the semiconductor substrate to diffuse the light and heavy dopants. In an example, the light dopant comprises P and the heavy dopant comprises As. In another example, the light dopant comprises P and the heavy dopant comprises Sb.
The semiconductor device of the present invention and the methods of fabricating a semiconductor device of the present invention provide fill materials that have high dopant concentrations and maintain a desired resistivity. Thin layers of fill material may be used in high aspect ratio trenches, thereby increasing the density of DRAM on a semiconductor chip. The present invention may also be used in stack structures (e.g., structures formed on top of a semiconductor substrate instead of within a trench formed in the semiconductor substrate). For example, a capacitor in a stack structure may be formed having a low resistivity capacitor fill material. The foregoing aspects, features and advantages of the present invention will be further appreciated when considered with reference to the following description of the preferred embodiments and accompanying drawings.